Offers New Capabilities for Automatic Error Detection in Simulink Models.
MathWorks today announced that Simulink Design Verifier now includes Polyspace analysis technology for automated error detection in Simulink models. Simulink Design Verifier 2.0 integrates Polyspace error detection with existing property proving and test generation capabilities to help reduce the time required to find and fix the root cause of design errors, decreasing the overall cost of verification and validation.
Engineers across the aerospace, automotive, medical, and industrial automation and machinery industries can now apply Model-Based Design with formal analysis methods provided by Simulink Design Verifier 2.0 to identify design errors in Simulink and Stateflow models without extensive testing or simulation.
Key product features include:
Detection of dead logic, integer and fixed-point overflows, division by zero, and assertion violation
Blocks and functions for modeling functional and safety requirements
Test vector generation from functional requirements and model coverage objectives
Property proving, with generation of violation examples for analysis and debugging
Fixed-point and floating-point model support
For a video demo overview of Simulink Design Verifier and the new capabilities, please visit mathworks.com/products/sldesignverifier.
Jul 8, 2011
- Delcam's new web site for PartMaker CAM system for production machining
- Surfware Appoints David Holding Company as New VAR in Bulgaria & Romania
- Panso Solutions of India Joins the Aras Partner Program
- COMET robot machining consortium meets at Fraunhofer
- EDS Technologies Signs MoU With Mar Baselios College Of Engineering
- Delcam launches DentSCAN dental scanner
- Rapiscan Uses Autodesk Vault to Effectively Collaborate on Security Products
- Delcam's ArtCAM speeds ice bar production
- InventorCAM 2012 makes its debut, reducing cycle times by up to 70% for Autodesk customers, with iMachining
- SigmaNEST Delivers Results to Tampa Bay Steel