MathWorks today announced the availability of EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench.
The introduction of FIL adds to the comprehensive set of HDL verification options that EDA Simulator Link supports for algorithms created in MATLAB and Simulink. FPGA-based verification provides significantly higher run-time performance than is possible with HDL simulators and increases confidence that the algorithm will work in the real world.
Key product features include the abilities to:
Verify HDL implementations of MATLAB code and Simulink models using FPGA development boards for both Spartan and Virtex class devices including the Virtex-6 ML605 development board.
Verify HDL implementations of MATLAB code and Simulink models using cosimulation with Mentor Graphics ModelSim, Mentor Graphics Questa, and Cadence Design Systems Incisive Enterprise Simulator
Generate TLM 2.0 components for use in SystemC virtual prototyping environments
Pricing and Availability
EDA Simulator Link is available immediately. U.S. list prices start at $2000.
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